As microelectronic components become smaller, more wiring and more signal traces must be miniaturized to fit onto smaller and smaller surface-area footprints of a package substrate. This trend has resulted in very fine conduction lines and high density wiring on the surface of a conventional substrate. But signal fidelity can suffer when the traces are very fine. Interference and other degradation can also occur when the pitch between lines is very fine for high density interconnects on a surface plane. Besides a signal layer, power and electrical ground connections may also need to be implemented the same horizontal surface of the substrate. When this surface “real estate” of the substrate becomes crowded, there may be a theoretical limit to further concentrating the high conductor count on a given top surface or bottom surface of the substrate. Conventional miniaturization needed to achieve a high density of conductive traces on a given top or bottom surface area of the substrate is also expensive.